1. Field of The Invention
The present invention relates generally to a nonvolatile CAM (Content-Addressable Memory), and more particularly, to a nonvolatile CAM capable of searching an address having information stored therein when the content of the information is specified, in addition to an ordinary memory function of specifying an address to read and write data.
2. Background Art
In recent computers, a part of data stored in a large capacity main memory is stored in a small capacity cache memory accessible at high speed, so that the access time is shortened.
FIG. 1 is a diagram showing a schematic structure of a cache memory system. In FIG. 1, data frequently accessed out of data stored in a main memory 51 is also stored in a cache memory 52. In such a cache memory system, it is necessary to determine which address in the main memory 51 corresponds to data to be stored in the cache memory 52. Thus, a CAM 53 is provided which can search information when the information is specified. An address in the main memory 51 corresponding to the data stored in the cache memory 52 is stored in the CAM 53. In the cache memory system shown in FIG. 1, if and when a CPU (Central Processing Unit 54) makes access to an address in the main memory 51, the address is first applied to the CAM 53. When the address is stored in the CAM 53, a cache hit signal CH is applied to a main controller 55. When the main controller 55 receives the cache hit signal CH, the CPU 54 makes access to the cache memory 52. On the other hand, when the address is not stored in the CAM 53, the CPU 54 makes access to the main memory 51.
FIG. 2 is an electric circuit diagram showing a memory cell in a conventional volatile CAM shown in ISSCC (Digest of Technical Paters, pp. 42 to 43, 1985).
In FIG. 2, the CAM comprises a CMOS (Complementary Metal Oxide Semiconductor) static RAM (Random Access Memory) portion A and a matching portion B. The matching portion B comprises four MOS transistors T7 to T10. The MOS transistors T7 and T8 are connected in series, and the MOS transistors T9 and T10 are connected in series. The MOS transistor T7 has its source connected to ground and its gate connected to a second storage node N2 in the CMOS static RAM portion A of a flip-flop. The MOS transistor T8 has its gate connected to a bit line BL constituting a bit line pair and its drain connected to a match line M.
The MOS transistor T9 has its source connected to ground and its gate connected to a first storage node N1 in the CMOS static RAM portion A. The MOS transistor T10 has its gate connected to a bit line BL and its drain connected to the match line M.
The CMOS static RAM portion A comprises four MOS transistors T3 to T6 as well as two MOS transistors T1 and T2 each serving as selecting transistor. The MOS transistor T1 has its source connected to the first storage node N1 in the CMOS static RAM portion A, its drain connected to the bit line BL and its gate connected to a word line WL. In addition, the MOS transistor T2 has its source connected to the second storage node N2 in the CMOS static RAM portion A, its drain connected to the bit line BL and its gate connected to the word line WL.
Description is now made on an operation of the conventional CAM shown in FIG. 2. First, at the time of searching, a potential on the word line WL is set to an "L" level, and the match line M is precharged to an "H" level. In addition, search data is applied to the bit line BL, and an inverted signal of the search data is applied to the bit line BL. For example, when it is desired to search "1", a potential on the bit line BL is set to the "H" level while a potential on the bit line BL is set to the "L" level. If "1" is stored in the CMOS static RAM portion A, that is, if a potential of the first storage node N1 is at the "H" level and a potential of the second storage node N2 is at the "L" level, the MOS transistors T9 and T8 are rendered conductive while the MOS transistors T7 and T10 are rendered non-conductive, so that a potential on the match line M remains at the "H" level. If "0" is stored in the CMOS static RAM portion A, that is, if the potential of the first storage node N1 is at the "L" level and potential of the second storage node N2 is at the "H" level, the MOS transistors T7 and T8 are rendered conductive, so that the match line M is discharged such that a potential thereon becomes a ground potential, which means mismatch.
The memory cell in the conventional CAM comprises the CMOS static RAM portion A of a flip-flop and the matching. portion B, as described above. Thus, if the power supply is turned off, data stored in the CMOS static RAM portion A is lost.